This function contains the processor’s second level cache and TLB characteristics for each core.
The EDX register contains the processor’s third level cache characteristics that are shared by all cores of the processor.
Note:
Use decodeL2orL3Assoc to get final result for any *Assoc field.
L2/L3 Cache and TLB Identifiers.
This function contains the processor’s second level cache and TLB characteristics for each core. The EDX register contains the processor’s third level cache characteristics that are shared by all cores of the processor.
Note: Use decodeL2orL3Assoc to get final result for any *Assoc field.
Specification: AMD